As conventional frequency multiply circuits, a configuration provided with a PLL (Phase Locked Loop) circuit or a DLL (Delay Locked Loop) circuit is employed. As is well known, the PLL circuit includes a phase comparator, a charge pump for converting the result of comparison by the phase comparator to a voltage, a loop filter for smoothing the output of the charge pump, and a VCO (voltage-controlled oscillator) for receiving a DC voltage from the loop filter as a control voltage and changing an oscillation frequency according to the control voltage. A frequency divider is provided in a feedback path between the output terminal of the VCO and the input terminal of the phase comparator, and the phase of a frequency-divided clock signal obtained by frequency dividing the output clock signal of the VCO by the frequency divider is compared with the phase of an input clock signal by the phase comparator. As described above, the frequency multiply circuit that uses the PLL circuit includes the phase comparator, which makes phase comparison with the waveform of an input signal. Thus, it requires time to achieve locking. As the frequency multiply circuit that uses the delay circuit (DLL) and includes the phase comparator, a description in Patent Document 1 is referred to.
FIGS. 7a and 7b show examples of a configuration of a conventional synchronous delay circuit (Synchronous Mirror Delay Circuit; also referred to as an “SMD”) (refer to Patent Document 2). As shown in FIG. 7a, the synchronous delay circuit includes an input buffer 903 (with a delay time thereof being td1), a dummy delay circuit 905 constituted from an input buffer dummy 905A (with a delay time thereof being td1) and a clock driver dummy 905B (with a delay time thereof being td2), a delay circuit line 901, a delay circuit line 902, and a clock driver 904 (with a delay time thereof being td2). The input buffer 903 receives an external clock signal. The delay circuit line 901 receives the output of the dummy delay circuit 905. When the clock signal input to the delay circuit line 901 has traveled a distance equivalent to one clock period, the clock signal is transferred to the delay circuit line 902 via a transfer circuit not shown. The signal propagates through the delay circuit line 902 in a direction opposite to that in the delay circuit line 901. The clock driver 904 receives the output of the delay circuit line 902. The clock driver 904 receives the output of the delay circuit line 902. The delay circuit line 901 is the delay circuit for period measurement, which measures one clock period of the clock signal. The delay circuit line 902 is the delay circuit for reproducing the delay time measured by the delay circuit line 901.
As shown in FIG. 7b, an external clock 906 (with a period thereof being tCK) propagates through the delay circuit line 901 for a time tV=tCK−(td1+td2), and is transferred to the delay circuit line 902. The external clock 906 propagates through the delay circuit line for the tV in a direction opposite to that in the delay circuit line 901, for output. Then, the external clock 906 is output from the clock driver 904 as an internal clock 907. After td1+td1+td2+2×{[tCK−(td1+td2)]+td2=2×tCK (two clock periods), the internal clock 907 is output. That is, the internal clock signal 907 delayed by twice the clock period tCK and synchronized with the external clock signal 906 is output.
As a frequency multiply circuit having a configuration provided with a plurality of the delay reproducing delay circuits of the synchronous delay circuit (indicated by reference numeral 902 in FIG. 7a), a description in Patent Document 3, which will be described hereinafter, is also referred to.
[Patent Document 1]
JP Patent Kokai Publication No. JP-A-10-335994 (FIGS. 1 and 5)
[Patent Document 2]
JP Patent No. 3434682 (FIG. 15)
[Patent Document 3]
JP Patent Kokai Publication No. JP-A-10-303713 (FIG. 1)